1. Field of the Invention
The present invention relates to memory devices and systems including memory management.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells. As the density increases in memory devices, and the floating gate memory cells get closer and closer together, interference between the charge stored in adjacent floating gates becomes a problem. This is limiting the ability to increase the density of flash memory based on floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate.
The typical flash memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a charge storage structure including a tunnel dielectric layer, the charge storage layer (floating gate or dielectric), and a blocking dielectric layer. According to the early conventional charge trapping memory designs referred to as SONOS devices, the source, drain and channel are formed in a silicon body which can be in a strip (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed of silicon oxide (O), and the gate comprises polysilicon (S).
Flash memory devices generally are implemented using NAND or NOR architectures, although others are known, including AND architectures. The NAND architecture is popular for its high density and high speed when applied to data storage applications. The NOR architecture is better suited to other applications, such as code storage, where random byte access is important. In a NAND architecture, the programming processes typically rely on Fowler-Nordheim (FN) tunneling, and require high voltages, such as on the order of 20 volts, and require high voltage transistors to handle them. The addition of high voltage transistors on integrated circuits, in combination with transistors used for logic and other data flow, introduces complexity in the manufacturing processes. This increased complexity in turn increases the costs of the devices.
Three-dimensional arrays of NAND memory feature even larger memory capacities in a relatively small volume. While programming a selected cell NAND array, nearby memory cells are subject to program disturb. Memory cells subject to program disturb include: a memory cell in the same NAND string; a memory cell accessed by the same word line and is in the same stack of semiconductor strips but is in a different layer of the stack; a memory cell accessed by the same word line and is in an adjacent stack of semiconductor strips though in the same layer; and a memory cell accessed by the same word line but is in an adjacent stack of semiconductor strips and in a different layer.
One approach to the reduction of program disturb is hot carrier injection, a memory technology suitable for low voltage programming operations, and which is configurable in a NAND architecture. Hot carrier injection in a NAND architecture has been previously described in U.S. application Ser. No. 12/797,994 filed on 10 Jun. 2010, which was published on 15 Dec. 2011 as US Patent Application Publication No 2011/0305088; and also in U.S. application Ser. No. 12/898,979 filed on 6 Oct. 2010, which was published on 5 Apr. 2012 as US Patent Application Publication No 2012/0081962, all of which are fully incorporated by reference.
Despite hot carrier injection, program disturb remains a problem in high density memory. It would be desirable to further improve on program disturb.